# $Id$
# AT86RF212 Template for generating the headerfile.
# License see in the HEADER section of this file
#
REGISTER
0x00 - - - - - - - - -
0x01 TRX_STATUS CCA_DONE CCA_STATUS - TRX_STATUS[4] TRX_STATUS[3] TRX_STATUS[2] TRX_STATUS[1] TRX_STATUS[0] 38,58,86
0x02 TRX_STATE TRAC_STATUS[2] TRAC_STATUS[1] TRAC_STATUS[0] TRX_CMD[4] TRX_CMD[3] TRX_CMD[2] TRX_CMD[1] TRX_CMD[0] 39,59
0x03 TRX_CTRL_0 PAD_IO[1] PAD_IO[0] PAD_IO_CLKM[1] PAD_IO_CLKM[0] CLKM_SHA_SEL CLKM_CTRL[2] CLKM_CTRL[1] CLKM_CTRL[0] 8119
0x04 TRX_CTRL_1 PA_EXT_EN IRQ_2_EXT_EN TX_AUTO_CRC_ON RX_BL_CTRL SPI_CMD_MODE[1] SPI_CMD_MODE[0] IRQ_MASK_MODE IRQ_POLARITY 20,26,60,
0x05 PHY_TX_PWR PA_BOOST GC_PA[1] GC_PA[0] TX_PWR[4] TX_PWR[3] TX_PWR[2] TX_PWR[1] TX_PWR[0] 106
0x06 PHY_RSSI RX_CRC_VALID RND_VALUE[1] RND_VALUE[0] RSSI[4] RSSI[3] RSSI[2] RSSI[1] RSSI[0] 78,80,
0x07 PHY_ED_LEVEL ED_LEVEL[7] ED_LEVEL[6] ED_LEVEL[5] ED_LEVEL[4] ED_LEVEL[3] ED_LEVEL[2] ED_LEVEL[1] ED_LEVEL[0] 83
0x08 PHY_CC_CCA CCA_REQUEST CCA_MODE[1] CCA_MODE[0] CHANNEL[4] CHANNEL[3] CHANNEL[2] CHANNEL[1] CHANNEL[0] 87,89,
0x09 CCA_THRES - - - - CCA_ED_THRES[3] CCA_ED_THRES[2] CCA_ED_THRES[1] CCA_ED_THRES[0] 88,90
0x0A - - - - - - - - -
0x0B SFD_VALUE SFD_VALUE[7] SFD_VALUE[6] SFD_VALUE[5] SFD_VALUE[4] SFD_VALUE[3] SFD_VALUE[2] SFD_VALUE[1] SFD_VALUE[0] 148
0x0C TRX_CTRL_2 RX_SAFE_MODE TRX_OFF_AVDD_EN - - BPSK_OQPSK SUB_MODE OQPSK_DATA_RATE[1] OQPSK_DATA_RATE[0] 95,114,
0x0D ANT_DIV ANT_SEL - - - - ANT_EXT_SW_EN ANT_CTRL[1] ANT_CTRL[0] 140
0x0E IRQ_MASK MASK_BAT_LOW MASK_TRX_UR MASK_AMI MASK_CCA_ED_READY MASK_TRX_END MASK_RX_START MASK_PLL_UNLOCK MASK_PLL_LOCK 25
0x0F IRQ_STATUS BAT_LOW TRX_UR AMI CCA_ED_READY TRX_END RX_START PLL_UNLOCK PLL_LOCK 26
0x10 VREG_CTRL AVREG_EXT AVDD_OK - - DVREG_EXT DVDD_OK - - 113
0x11 BATMON - - BATMON_OK BATMON_HR BATMON_VTH[3] BATMON_VTH[2] BATMON_VTH[1] BATMON_VTH[0] 116
0x12 XOSC_CTRL XTAL_MODE[3] XTAL_MODE[2] XTAL_MODE[1] XTAL_MODE[0] XTAL_TRIM[3] XTAL_TRIM[2] XTAL_TRIM[1] XTAL_TRIM[0] 121
0x13 CC_CTRL_0 CC_NUMBER[7] CC_NUMBER[6] CC_NUMBER[5] CC_NUMBER[4] CC_NUMBER[3] CC_NUMBER[2] CC_NUMBER[1] CC_NUMBER[0] 125
0x14 CC_CTRL_1 - - - - - CC_BAND[2] CC_ BAND[1] CC_ BAND[0] 125
0x15 RX_SYN RX_PDT_DIS - - - RX_PDT_LEVEL[3] RX_PDT_LEVEL[2] RX_PDT_LEVEL[1] RX_PDT_LEVEL[0] 99
0x16 RF_CTRL_0 PA_LT[1] PA_LT[0] - - - - GC_TX_OFFS[1] GC_TX_OFFS[0] 105
0x17 XAH_CTRL_1 CSMA_LBT_MODE - AACK_FLTR_RES_FT AACK_UPLD_RES_FT - AACK_ACK_TIME AACK_PROM_MODE - 61,72,90
0x18 FTN_CTRL FTN_START - - - - - - - 127
0x19 RF_CTRL_1 RF_MC[3] RF_MC[2] RF_MC[1] RF_MC[0] - - - - 99
0x1A PLL_CF PLL_CF_START - - - - - - - 126
0x1B PLL_DCU PLL_DCU_START - - - - - - - 126
0x1C PART_NUM PART_NUM[7] PART_NUM[6] PART_NUM[5] PART_NUM[4] PART_NUM[3] PART_NUM[2] PART_NUM[1] PART_NUM[0] 21
0x1D VERSION_NUM VERSION_NUM[7] VERSION_NUM[6] VERSION_NUM[5] VERSION_NUM[4] VERSION_NUM[3] VERSION_NUM[2] VERSION_NUM[1] VERSION_NUM[0] 21
0x1E MAN_ID_0 MAN_ID_0[7] MAN_ID_0[6] MAN_ID_0[5] MAN_ID_0[4] MAN_ID_0[3] MAN_ID_0[2] MAN_ID_0[1] MAN_ID_0[0] 21
0x1F MAN_ID_1 MAN_ID_1[7] MAN_ID_1[6] MAN_ID_1[5] MAN_ID_1[4] MAN_ID_1[3] MAN_ID_1[2] MAN_ID_1[1] MAN_ID_1[0] 22
0x20 SHORT_ADDR_0 SHORT_ADDR_0[7] SHORT_ADDR_0[6] SHORT_ADDR_0[5] SHORT_ADDR_0[4] SHORT_ADDR_0[3] SHORT_ADDR_0[2] SHORT_ADDR_0[1] SHORT_ADDR_0[0] 73
0x21 SHORT_ADDR_1 SHORT_ADDR_1[7] SHORT_ADDR_1[6] SHORT_ADDR_1[5] SHORT_ADDR_1[4] SHORT_ADDR_1[3] SHORT_ADDR_1[2] SHORT_ADDR_1[1] SHORT_ADDR_1[0] 73
0x22 PAN_ID_0 PAN_ID_0[7] PAN_ID_0[6] PAN_ID_0[5] PAN_ID_0[4] PAN_ID_0[3] PAN_ID_0[2] PAN_ID_0[1] PAN_ID_0[0] 73
0x23 PAN_ID_1 PAN_ID_1[7] PAN_ID_1[6] PAN_ID_1[5] PAN_ID_1[4] PAN_ID_1[3] PAN_ID_1[2] PAN_ID_1[1] PAN_ID_1[0] 73
0x24 IEEE_ADDR_0 IEEE_ADDR_0[7] IEEE_ADDR_0[6] IEEE_ADDR_0[5] IEEE_ADDR_0[4] IEEE_ADDR_0[3] IEEE_ADDR_0[2] IEEE_ADDR_0[1] IEEE_ADDR_0[0] 74
0x25 IEEE_ADDR_1 IEEE_ADDR_1[7] IEEE_ADDR_1[6] IEEE_ADDR_1[5] IEEE_ADDR_1[4] IEEE_ADDR_1[3] IEEE_ADDR_1[2] IEEE_ADDR_1[1] IEEE_ADDR_1[0] 74
0x26 IEEE_ADDR_2 IEEE_ADDR_2[7] IEEE_ADDR_2[6] IEEE_ADDR_2[5] IEEE_ADDR_2[4] IEEE_ADDR_2[3] IEEE_ADDR_2[2] IEEE_ADDR_2[1] IEEE_ADDR_2[0] 74
0x27 IEEE_ADDR_3 IEEE_ADDR_3[7] IEEE_ADDR_3[6] IEEE_ADDR_3[5] IEEE_ADDR_3[4] IEEE_ADDR_3[3] IEEE_ADDR_3[2] IEEE_ADDR_3[1] IEEE_ADDR_3[0] 74
0x28 IEEE_ADDR_4 IEEE_ADDR_4[7] IEEE_ADDR_4[6] IEEE_ADDR_4[5] IEEE_ADDR_4[4] IEEE_ADDR_4[3] IEEE_ADDR_4[2] IEEE_ADDR_4[1] IEEE_ADDR_4[0] 75
0x29 IEEE_ADDR_5 IEEE_ADDR_5[7] IEEE_ADDR_5[6] IEEE_ADDR_5[5] IEEE_ADDR_5[4] IEEE_ADDR_5[3] IEEE_ADDR_5[2] IEEE_ADDR_5[1] IEEE_ADDR_5[0] 75
0x2A IEEE_ADDR_6 IEEE_ADDR_6[7] IEEE_ADDR_6[6] IEEE_ADDR_6[5] IEEE_ADDR_6[4] IEEE_ADDR_6[3] IEEE_ADDR_6[2] IEEE_ADDR_6[1] IEEE_ADDR_6[0] 75
0x2B IEEE_ADDR_7 IEEE_ADDR_7[7] IEEE_ADDR_7[6] IEEE_ADDR_7[5] IEEE_ADDR_7[4] IEEE_ADDR_7[3] IEEE_ADDR_7[2] IEEE_ADDR_7[1] IEEE_ADDR_7[0] 75
0x2C XAH_CTRL_0 MAX_FRAME_RETRIES[3] MAX_FRAME_RETRIES[2] MAX_FRAME_RETRIES[1] MAX_FRAME_RETRIES[0] MAX_CSMA_RETRIES[2] MAX_CSMA_RETRIES[1] MAX_CSMA_RETRIES[0] SLOTTED_OPERATION 63
0x2D CSMA_SEED_0 CSMA_SEED_0[7] CSMA_SEED_0[6] CSMA_SEED_0[5] CSMA_SEED_0[4] CSMA_SEED_0[3] CSMA_SEED_0[2] CSMA_SEED_0[1] CSMA_SEED_0[0] 63
0x2E CSMA_SEED_1 AACK_FVN_MODE[1] AACK_FVN_MODE[0] AACK_SET_PD AACK_DIS_ACK AACK_I_AM_COORD CSMA_SEED_1[2] CSMA_SEED_1[1] CSMA_SEED_1[0] 64,75
0x2F CSMA_BE MAX_BE[3] MAX_BE[2] MAX_BE[1] MAX_BE[0] MIN_BE[3] MIN_BE[2] MIN_BE[1] MIN_BE[0] 65
CONST
TRX_STATUS P_ON 0
TRX_STATUS BUSY_RX 1
TRX_STATUS BUSY_TX 2
TRX_STATUS RX_ON 6
TRX_STATUS TRX_OFF 8
TRX_STATUS PLL_ON 9
TRX_STATUS TRX_SLEEP 15
TRX_STATUS BUSY_RX_AACK 17
TRX_STATUS BUSY_TX_ARET 18
TRX_STATUS RX_AACK_ON 22
TRX_STATUS TX_ARET_ON 25
TRX_STATUS RX_ON_NOCLK 28
TRX_STATUS RX_AACK_ON_NOCLK 29
TRX_STATUS BUSY_RX_AACK_NOCLK 30

TRAC_STATUS TRAC_SUCCESS 0
TRAC_STATUS TRAC_SUCCESS_DATA_PENDING 1
TRAC_STATUS TRAC_SUCCESS_WAIT_FOR_ACK 2
TRAC_STATUS TRAC_CHANNEL_ACCESS_FAILURE 3
TRAC_STATUS TRAC_NO_ACK 5
TRAC_STATUS TRAC_INVALID 7

TRX_CMD CMD_NOP 0
TRX_CMD CMD_TX_START 2
TRX_CMD CMD_FORCE_TRX_OFF 3
TRX_CMD CMD_RX_ON 6
TRX_CMD CMD_TRX_OFF 8
TRX_CMD CMD_PLL_ON 9
TRX_CMD CMD_RX_AACK_ON 22
TRX_CMD CMD_TX_ARET_ON 25

PAD_IO_CLKM CLKM_2mA 0
PAD_IO_CLKM CLKM_4mA 1
PAD_IO_CLKM CLKM_6mA 2
PAD_IO_CLKM CLKM_8mA 3

CLKM_CTRL CLKM_no_clock 0
CLKM_CTRL CLKM_1MHz 1
CLKM_CTRL CLKM_2MHz 2
CLKM_CTRL CLKM_4MHz 3
CLKM_CTRL CLKM_8MHz 4
CLKM_CTRL CLKM_16MHz 5
PART_NUM RF212A_PART_NUM 7
VERSION_NUM RF212A_VERSION_NUM 1
HEADER
/* Copyright (c) 2008 Axel Wachtler
   All rights reserved.

   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions
   are met:

   * Redistributions of source code must retain the above copyright
     notice, this list of conditions and the following disclaimer.
   * Redistributions in binary form must reproduce the above copyright
     notice, this list of conditions and the following disclaimer in the
     documentation and/or other materials provided with the distribution.
   * Neither the name of the authors nor the names of its contributors
     may be used to endorse or promote products derived from this software
     without specific prior written permission.

   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */

/* $Id$ */
/**
 * @file
 * @brief AT86RF212 - 700/868/900MHz IEEE 802.15.4-2006-Transceiver.
 */
#ifndef AT86RF212_H
#define AT86RF212_H (1)
/* === Includes ============================================================== */

/* === Externals ============================================================= */

/* === Types ================================================================= */

typedef uint8_t trx_ramaddr_t;
typedef uint8_t trx_regval_t;
typedef uint8_t trx_regaddr_t;

/* === Macros ================================================================ */

FOOTER
/** name string of the radio */
#define RADIO_NAME "AT86RF212"
/** contents of the RG_PART_NUM register */
#define RADIO_PART_NUM (RF212A_PART_NUM)
/** contents of the RG_VERSION_NUM register */
#define RADIO_VERSION_NUM (RF212A_VERSION_NUM)

/** SPI command code for register write */
#define TRX_CMD_RW           (_BV(7) | _BV(6))
/** SPI command code for register read */
#define TRX_CMD_RR           (_BV(7))
/** SPI command code for frame write */
#define TRX_CMD_FW           (_BV(6) | _BV(5))
/** SPI command code for frame read */
#define TRX_CMD_FR           (_BV(5))
/** SPI command code for sram write */
#define TRX_CMD_SW           (_BV(6))
/** SPI command code for sram read */
#define TRX_CMD_SR           (0)

#define TRX_CMD_RADDR_MASK   (0x3f)

/** duration while reset=low is asserted */
#define TRX_RESET_TIME_US    (6)

/** duration transceiver reaches TRX_OFF for the first time */
#define TRX_INIT_TIME_US     (510)

/** maximum duration, which PLL needs to lock */
#define TRX_PLL_LOCK_TIME_US     (180)


/** duration of a CCA measurement */
#define TRX_CCA_TIME_US     (140)

/** Mask for PLL lock interrupt */
#define TRX_IRQ_PLL_LOCK   _BV(0)

/** Mask for PLL unlock interrupt */
#define TRX_IRQ_PLL_UNLOCK _BV(1)

/** Mask for RX Start interrupt */
#define TRX_IRQ_RX_START   _BV(2)

/** Mask for RX/TX end interrupt */
#define TRX_IRQ_TRX_END    _BV(3)

/** Mask for CCA_ED interrupt */
#define TRX_IRQ_CCA_ED     _BV(4)

/** Mask for AMI interrupt */
#define TRX_IRQ_AMI        _BV(5)

/** Mask for RX/TX underrun interrupt */
#define TRX_IRQ_UR         _BV(6)

/** Mask for battery low interrupt */
#define TRX_IRQ_BAT_LOW    _BV(7)

/** TX ARET status for successful transmission */
#define TRAC_SUCCESS (0)
/** TX ARET status for unsuccessful transmission due to no channel access */
#define TRAC_CHANNEL_ACCESS_FAILURE (3)
/** TX ARET status for unsuccessful transmission due no ACK frame was received */
#define TRAC_NO_ACK (5)


/** lowest supported channel number */
#define TRX_MIN_CHANNEL (0)

/** highest supported channel number */
#define TRX_MAX_CHANNEL (10)

/** number of channels */
#define TRX_NB_CHANNELS (11)

/**
 * @brief Mask for supported channels of this radio.
 * The AT86RF212 supports channels 0 ... 10 of IEEE 802.15.4
 * (currently no support for free configurable frequencies here)
 */
#define TRX_SUPPORTED_CHANNELS  (0x00007ffUL)

/**
 * @brief Mask for supported channel pages (a.k.a. modulation schemes) of this radio.
 * The AT86RF230 supports channel page ???? OQPSK_250
 */
#define TRX_SUPPORTED_PAGES     (42)
#define TRX_SUPPORTS_BAND_700 (1)
#define TRX_SUPPORTS_BAND_800 (1)
#define TRX_SUPPORTS_BAND_900 (1)

/** Rate code for BPSK20, xx kchip/s, yy kbit/s */
#define TRX_BPSK20    (0)

/** Rate code for BPSK40, xx kchip/s, yy kbit/s */
#define TRX_BPSK40    (4)

/** Rate code for OQPSK100, xx kchip/s, yy kbit/s */
#define TRX_OQPSK100  (8)

/** Rate code for OQPSK200, xx kchip/s, yy kbit/s */
#define TRX_OQPSK200  (9)

/** Rate code for OQPSK400, xx kchip/s, yy kbit/s */
#define TRX_OQPSK400  (10)
#define TRX_OQPSK400_1  (11)

/** Rate code for OQPSK250, xx kchip/s, yy kbit/s */
#define TRX_OQPSK250  (12)

/** Rate code for OQPSK500, xx kchip/s, yy kbit/s */
#define TRX_OQPSK500  (13)

/** Rate code for OQPSK1000, xx kchip/s, yy kbit/s */
#define TRX_OQPSK1000 (14)
#define TRX_OQPSK1000_1 (15)
/** undefined data rate */
#define TRX_NONE      (255)

#endif /* ifndef AT86RF212_H */
