data0		.SET	00600h
data1		.SET	00601h
data2		.SET	00602h
data3		.SET	00603h
data4		.SET	00604h
data5		.SET	00605h

temp		.SET	00606h
ser_dat		.SET	00607h

key0		.SET	00608h
key1		.SET	00609h
key2		.SET	0060Ah
key3		.SET	0060Bh
key4		.SET	0060Ch
key5		.SET	0060Dh
key6		.SET	0060Eh
key7		.SET	0060Fh

e_key_begin	.SET	00610h
e_key_end	.SET	00640h

shift0		.SET	00670h
shift1		.SET	00671h
shift2		.SET	00672h
shift3		.SET	00673h
shift4		.SET	00674h
shift5		.SET	00675h
shift6		.SET	00676h
shift7		.SET	00677h

; ---------------------------------------------------------------------------

		.DS	00608h

init_test_key:	.WORD	00000h, 01111h, 02222h, 03333h
		.WORD	04444h, 05555h, 06666h, 07777h


		.DS	00670h

init_test_shft:	.WORD	00000h, 00000h, 00000h, 00000h
		.WORD	00000h, 00000h, 00000h, 00000h

; ---------------------------------------------------------------------------

		.PS	0FA00h
		.ENTRY
RESET:		B	start

		.PS	0FA0Ah
B0RINT:		B	RINT

; -----------------------------------------------------------------------------

		.PS	0FB00h

start:		SPM	0
		RSXM

		FORT	1
		RTXM
		SFSM

		LDPK	0Ch

		CALL	idea_key_exp, *, 7

		LDPK	00h
		LARP	00h
		LARK	AR0,0
		LACK	010h
		SACL	004h
		EINT

loop:		B	loop

; -----------------------------------------------------------------------------

RINT:		LDPK	00h
		SST1	060h
		LAC	000h
		LDPK	0Ch

		SACL	ser_dat

		CALL	idea_cyk, *, 7

		LAC	ser_dat
		CALL	idea_shift, *, 7
		XOR	data0

		LDPK	00h
		SACL	001h
		LST1	060h
		EINT
		RET

; ---------------------------------------------------------------------------

idea_key_exp:	LRLK	AR7,e_key_begin		; idea_key
		LRLK	AR0,e_key_end
idea_key_exp_3:
		RPTK	007h
		BLKD	key0, *+

		LARK	AR2, 018h
		LARP	2
idea_key_exp_2:	ZALH	key0
		ROL

		ZALH	key6
		OR	key7
		ROL
		SACL	key7
		SACH	key6

		ZALH	key4
		OR	key5
		ROL
		SACL	key5
		SACH	key4

		ZALH	key2
		OR	key3
		ROL
		SACL	key3
		SACH	key2

		ZALH	key0
		OR	key1
		ROL
		SACL	key1
		SACH	key0

		BANZ	idea_key_exp_2, *-

		LARP	7
		CMPR	02
		BBZ	idea_key_exp_3

	;	RET

		LRLK	AR7,e_key_begin		; idea_key
		LRLK	AR0,e_key_end
idea_key_exp_1:
		LAC	*
		XORK	00DEAh
		SACL	*+

		CMPR	02
		BBZ	idea_key_exp_1

		RET

; ---------------------------------------------------------------------------

idea_shift:	ANDK	000FFh

		LRLK	AR7, 00676h
		RPTK	006h
		DMOV	*-
		SACL	shift0

		RET

; ---------------------------------------------------------------------------

idea_cyk:	LT	shift7
		MPYK	00100h
		PAC
		OR	shift6
		SACL	data3

		LT	shift5
		MPYK	00100h
		PAC
		OR	shift4
		SACL	data2

		LT	shift3
		MPYK	00100h
		PAC
		OR	shift2
		SACL	data1

		LT	shift1
		MPYK	00100h
		PAC
		OR	shift0
		SACL	data0

; ---------------------------------------------------------------------------

idea_start:	LRLK	AR7,e_key_begin		; idea_key
		LRLK	AR0,e_key_end

idea_loop:	LAC	*
		BZ	idea_00
		LAC	data0
		BZ	idea_01
		LT	data0
		MPYU	*+
		PAC
		SPH	temp
		SUBH	temp
		SUB	temp
		BNC	idea_02
		B	idea_03
idea_00:	LAC	data0
		B	idea_04, *+
idea_01:	LAC	*+
idea_04:	NEG
idea_02:	ADDK	001h
idea_03:	SACL	data0

		LAC	data1
		ADD	*+
		SACL	data1

		LAC	data2
		ADD	*+
		SACL	data2

		LAC	*
		BZ	idea_10
		LAC	data3
		BZ	idea_11
		LT	data3
		MPYU	*+
		PAC
		SPH	temp
		SUBH	temp
		SUB	temp
		BNC	idea_12
		B	idea_13
idea_10:	LAC	data3
		B	idea_14, *+
idea_11:	LAC	*+
idea_14:	NEG
idea_12:	ADDK	001h
idea_13:	SACL	data3

		LAC	data0
		XOR	data2
		SACL	data4

		LAC	data1
		XOR	data3
		SACL	data5

		LAC	*
		BZ	idea_20
		LAC	data4
		BZ	idea_21
		LT	data4
		MPYU	*+
		PAC
		SPH	temp
		SUBH	temp
		SUB	temp
		BNC	idea_22
		B	idea_23
idea_20:	LAC	data4
		B	idea_24, *+
idea_21:	LAC	*+
idea_24:	NEG
idea_22:	ADDK	001h
idea_23:	SACL	data4

		ADD	data5
		SACL	data5

		LAC	*
		BZ	idea_30
		LAC	data5
		BZ	idea_31
		LT	data5
		MPYU	*+
		PAC
		SPH	temp
		SUBH	temp
		SUB	temp
		BNC	idea_32
		B	idea_33
idea_30:	LAC	data5
		B	idea_34, *+
idea_31:	LAC	*+
idea_34:	NEG
idea_32:	ADDK	001h
idea_33:	SACL	data5

		ADD	data4
		SACL	data4

		LAC	data0
		XOR	data5
		SACL	data0

		LAC	data1
		XOR	data4
		SACL	data1

		LAC	data2
		XOR	data5
		SACL	data2

		LAC	data3
		XOR	data4
		SACL	data3

		LAC	data2
		DMOV	data1
		SACL	data1

		CMPR	1
		BBNZ	idea_loop

		LAC	data2
		DMOV	data1
		SACL	data1

		LAC	*
		BZ	idea_40
		LAC	data0
		BZ	idea_41
		LT	data0
		MPYU	*+
		PAC
		SPH	temp
		SUBH	temp
		SUB	temp
		BNC	idea_42
		B	idea_43
idea_40:	LAC	data0
		B	idea_44, *+
idea_41:	LAC	*+
idea_44:	NEG
idea_42:	ADDK	001h
idea_43:	SACL	data0

		LAC	data1
		ADD	*+
		SACL	data1

		LAC	data2
		ADD	*+
		SACL	data2

		LAC	*
		BZ	idea_50
		LAC	data3
		BZ	idea_51
		LT	data3
		MPYU	*+
		PAC
		SPH	temp
		SUBH	temp
		SUB	temp
		BNC	idea_52
		B	idea_53
idea_50:	LAC	data3
		B	idea_54, *+
idea_51:	LAC	*+
idea_54:	NEG
idea_52:	ADDK	001h
idea_53:	SACL	data3

		RET

; ---------------------------------------------------------------------------